The present invention relates to a semiconductor integrated circuit device, and more particularly to techniques which are effective when applied to the cell layout of a logic LSI that is fabricated in accordance with a master slice scheme.
A gate array being a typical example of a logic LSI which is fabricated in accordance with the master slice scheme, usually has a cell layout wherein basic cells are arranged in a matrix array inside peripheral circuits which function as interfaces with the exterior. Various logic circuits, such as inverters, AND (NAND) gates, OR (NOR) gates and flip-flops, are formed by properly combining and connecting the basic cells. That is, the gate array permits the required logic circuits to be formed by altering the patterns of wiring on a master wafer and therefore permits many kinds of products to be developed in a short period of time. Besides, the aforementioned logic circuits include also circuits, for example, a clock buffer circuit and a delay circuit, each of which requires a driving power level higher than that of the general logic circuit. In case of forming such a circuit, the high driving power is secured ordinarily by connecting some of the basic cells in parallel.